View RF2905_1161484.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

RF2905
11
Typical Applications
* Wireless Meter Reading * Keyless Entry Systems * 433/868/915MHz ISM Band Systems * Wireless Data Transceiver * Wireless Security Systems * Battery Powered Portable Devices
433/868/915MHZ FM/FSK/ASK/OOK TRANSCEIVER
Product Description
The RF2905 is a monolithic integrated circuit intended for use as a low cost FM transceiver. The device is provided in 7mmx7mm, 48-lead plastic LQFP packaging and is designed to provide a fully functional FM transceiver. The chip is intended for linear (AM, FM) or digital (ASK, FSK, OOK) applications in the North American 915MHz ISM band and European 433MHz and 868MHz ISM bands. The integrated VCO, dual modulus/dual divide (128/129 or 64/65) prescaler, and reference oscillator require only the addition of an external crystal to provide a complete phase-locked oscillator.
9.00 + 0.20 sq.
0.35 0.25
0.50 7.00 + 0.10 sq.
0.22 + 0.05
1.40 + 0.05
Dimensions in mm.
7 MAX 0 MIN
0.60 + 0.15 0.10
0.127
Optimum Technology Matching(R) Applied
u
Package Style: LQFP-48, 7x7
Si BJT Si Bi-CMOS
RESNTR-
GaAs HBT SiGe HBT
LOCK DET LOOP FLT RESNTR+
GaAs MESFET Si CMOS
Features
* Fully Monolithic Integrated Transceiver * 2.7V to 5.0V Supply Voltage * Narrow Band and Wide Band FM/FSK * 300MHz to 1000MHz Frequency Range * 10dB Cascaded Noise Figure * 10mW Output Power at 433MHz
11
TRANSCEIVERS
LVL ADJ
OSC B1
47 Gain Control TX OUT RX IN 3 5
34
31
30
41
42
43 Lock Detector
40
39
38
Phase Detector & Charge Pump
Ref Select
OSC B2 37 OSC SEL 45 PRESCL OUT 36 MOD CTRL 35 DIV CTRL 24 RSSI 25 FM OUT 26 DATA OUT
MOD IN
VREF P
LNA OUT MIX IN MIX OUT+ MIX OUT-
7 9 11 12
Prescaler 128/129 or 64/65
Linear RSSI
OSC E
13 IF1 IN+
14 IF1 IN-
15 IF1 BP+
16 IF1 BP-
17 IF1 OUT
18 IF2 IN
20 VREF IF
21 IF2 BP+
22 IF2 BP-
28 IF2 OUT
27 DEMOD IN
23 MUTE
Ordering Information
RF2905 RF2905 PCBA-L RF2905 PCBA-M RF2905 PCBA-H 433/868/915MHz FM/FSK/ASK/OOK Transceiver Fully Assembled Evaluation Board (433MHz) Fully Assembled Evaluation Board (868MHz) Fully Assembled Evaluation Board (915MHz) Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
Functional Block Diagram
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA
Rev B11 010516
11-53
RF2905
Absolute Maximum Ratings Parameter
Supply Voltage Control Voltages Input RF Level Output Load VSWR Operating Ambient Temperature Storage Temperature
Ratings
-0.5 to +5.5 -0.5 to +5.0 +10 50:1 -40 to +85 -40 to +150
Unit
VDC VDC dBm C C Caution! ESD sensitive device.
RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter
Overall
RF Frequency Range
Specification Min. Typ. Max.
300 to 1000 300 to 1000 64/65 or 128/129 50 -75 -100
Unit
MHz MHz dBc/Hz dBc/Hz
Condition
T=25 C, VCC =3.6V, Freq=915MHz
VCO and PLL Section
VCO Frequency Range Prescaler divide ratio Prescaler Output Impedance PLL Phase Noise
Freq=915MHz, 10kHz Offset, 5kHz Loop Bandwidth Freq=915MHz, 100kHz Offset, 5kHz loop Bandwidth
Reference Frequency Crystal RS Charge Pump Current
TBD 50 -40 2
17 100 +40
MHz A MHz dBm dBm dB dB/V kHz Freq=433MHz Freq=915MHz
Transmit Section
Max Modulation Frequency Min Modulation Frequency Maximum Power Level Power Control Range Power Control Sensitivity Max FM Deviation Set by loop filter bandwidth +7 +10 0 +3 8 12 10 200
11
TRANSCEIVERS
Antenna Port Impedance Antenna Port VSWR Modulation Input Impedance Harmonics Spurious
50 1.5:1 4 -23
Instantaneous frequency deviation is inversely proportional with the modulation voltage TX ENABL="1". RX ENABL="0" TX Mode
k dBc dBc MHz dB dB dB dBm dBm dBm dBm V mV/dB dB
Compliant to Part 15.249 and I-ETS 300 220
Overall Receive Section
Frequency Range Cascaded Voltage Gain Cascaded Noise Figure Cascaded Input IP3 RX Sensitivity LO Leakage RSSI DC Output Range RSSI Sensitivity RSSI Dynamic Range -95 300 to 1000 35 23 10 -31 -26 -101 -70 0.5 to 2.5 70 25 80 Freq=433MHz Freq=915MHz Freq=433MHz Freq=915MHz IF BW =180kHz, Freq=915MHz, S/N=8dB RLOAD =51k
11-54
Rev B11 010516
RF2905
Parameter
LNA
Voltage Gain Noise Figure Input IP3 Input P1dB Antenna Port Impedance Antenna Port VSWR Output Impedance 23 16 4.8 5.5 -27 -20 -37 -30 50 1.5:1 Open Collector Open Collector 8 7 10 17 -21 -17 -31 -28 dB dB dB dB dBm dBm dBm dBm VPP 25 MHz dB dB MHz dB k k kHz kHz VCC -0.3 V dB dB dB dB dBm dBm dBm dBm 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz RX ENABL="1". TX ENABL="0" RX Mode 433MHz 915MHz Single-ended configuration 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz 433MHz 915MHz Balanced
Specification Min. Typ. Max.
Unit
Condition
Mixer
Conversion Voltage Gain Noise Figure (SSB) Input IP3 Input P1dB Maximum Output Voltage
First IF Section
IF Frequency Range Voltage Gain Noise Figure IF1 Input Impedance IF1 Output Impedance 0.1 10.7 34 13 330 330 10.7 60 330 1 10 500 >1 IF=10.7MHz, ZL =330
Second IF Section
IF Frequency Range Voltage Gain IF2 Input Impedance IF2 Output Impedance Demod Input Impedance FM Output Impedance Data Output Impedance FM Output Bandwidth Data Output Bandwidth Data Output Level 0.1 25 IF=10.7MHz At IF2 OUT- pin
11
TRANSCEIVERS
500 500 0.3
FM Output DC Level FM Output AC Level
2.6 200
V mVPP
3dB Bandwidth, Dependent upon IF bandwidth and Discriminator. 3dB Bandwidth, ZLOAD=1M || 3pF; Dependent upon IF bandwidth and Discriminator. ZLOAD=1M || 3pF; Output voltage is proportional with the instantaneous frequency deviation. ZLOAD>10k ZLOAD>10k
Rev B11 010516
11-55
RF2905
Parameter
Power Down Control
Logical Controls "ON" Logical Controls "OFF" Control Input Impedance Turn On Time Turn Off Time RX to TX and TX to RX Time 2.0 1.0 25k 4 4 4 3.6 2.7 to 5.0 25 10 9 V V ms ms ms V V mA mA mA A Voltage supplied to the input Voltage supplied to the input Reference Crystal=7.075MHz Dependent upon reference crystal. Higher frequencies reduce turn on/off times Specifications Operating limits TX Mode, LVL ADJ=3.6V TX Mode, LVL ADJ=0V RX Mode Power Down Mode which sets: PLL ENABL, TX ENABL, RX ENABL, LVL ADJ, OSC SEL, and MUTE=0V PLL Only Mode
Specification Min. Typ. Max.
Unit
Condition
Power Supply
Voltage Current Consumption 22 8 7
34.5 13.5 12 1
5.3
8
10
mA
11
TRANSCEIVERS
11-56
Rev B11 010516
RF2905
Pin 1 Function RX ENABL Description
Enable pin for the receiver circuits. RX ENABL>2.0V powers up all receiver functions. RX ENABL<1.0V turns off all receiver functions except the PLL functions and the RF mixer.
Interface Schematic
50 k RX ENABL
2
TX ENABL
Enables the transmitter circuits. TX ENABL>2.0V powers up all transmitter functions. TX ENABL<1.0V turns off all transmitter functions except the PLL functions.
20 k TX ENABL 40 k
3
TX OUT
RF output pin for the transmitter electronics. TX OUT output impedance is a low impedance when the transmitter is enabled. TX OUT is a high impedance when the transmitter is disabled.
20
VCC
TX OUT
4 5
GND2 RX IN
Ground connection for the 40dB IF limiting amplifier and Tx PA functions. Keep traces physically short and connect immediately to ground plane for best performance. RF input pin for the receiver electronics. RX IN input impedance is a low impedance when the transmitter is enabled. RX IN is a high impedance when the receiver is disabled.
500
RX IN
6 7 8 9
GND1 LNA OUT GND3 MIX IN
Ground connection for RF receiver functions. Keep traces physically short and connect immediately to ground plane for best performance. Output pin for the receiver RF low noise amplifier. This pin is an open collector output and requires an external pull up coil to provide bias and tune the LNA output. Same as pin 4. RF input to the RF Mixer. An LC matching network between LNA OUT and MIX IN can be used to connect the LNA output to the RF mixer input in applications where an image filter is not needed or desired.
VCC
LNA OUT
11
MIX IN
10 11
GND5 MIX OUT+
12
MIX OUT-
GND5 is the ground connection shared by the input stage of the transmit power amplifier and the receiver RF mixer. Complementary (with respect to pin 12) IF output from the RF mixer. MIX OUT+ Interfaces directly to 10.7MHz ceramic IF filters as shown in the application schematic. A pull-up inductor and series matching capacitor should be used to present a 330 termination impedance to the 15 pF ceramic filter. Alternately, an IF tank can be used to tailor the IF freGND5 quency and bandwidth to meet the needs of a given application. IF output from the RF mixer. For a balanced mixer output, pull-up induc- See pin 11. tors from pin 11 and 12 to VCC and a capacitor between the pins should be used. The sum of the total pull-up inductance should be used to resonate the capacitor between pins 11 and 12. DC blocking capacitors of 10nF can then be used to connect the balanced output to IF1 IN+ (pin 13) and IF1 IN- (pin 14).
MIX OUT-
15 pF GND5
Rev B11 010516
11-57
TRANSCEIVERS
GND5
RF2905
Pin 13 Function IF1 IN+ Description
Balanced IF input to the 40dB limiting amplifier strip. A 10nF DC blocking capacitor is required on this input.
Interface Schematic
IF1 BP+ 60 k 330 IF1 IN+ IF1 BP60 k 330 IF1 IN-
14 15 16 17
IF1 INIF1 BP+ IF1 BPIF1 OUT
Functionally the same as pin 13 except inverting node amplifier input. In single-ended applications, this input should be bypassed directly to ground through a 10nF capacitor. DC feedback node for the 40dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. Same as pin 15. IF output from the 40dB limiting amplifier. The IF1 OUT output presents a nominal 330 output resistance and interfaces directly to 10.7MHz ceramic filters.
See pin 13.
See pin 13. See pin 13.
IF1 OUT
18
IF2 IN
Balanced IF input to the 60dB limiting amplifier strip. A 10nF DC blocking capacitor is required on this input. The IF2 IN input presents a nominal 330 input resistance and interfaces directly to 10.7MHz ceramic filters.
IF2 IN
IF2 BP+ 60 k 330
IF2 BP60 k 330
19 20
GND6 VREF IF IF2 BP+ IF2 BPMUTE
11
TRANSCEIVERS
21 22 23
Ground connection for 60dB IF limiting amplifier. Keep traces physically short and connect immediately to ground plane for best performance. DC voltage reference for the IF limiting amplifiers. A 10nF capacitor from this pin to ground is required. DC feedback node for the 60dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. Same as pin 21. This pin is used to mute the data output (DATA OUT). MUTE>2.0V turns the DATA OUT signal on. MUTE<1.0V turns the DATA OUT signal off. The MUTE signal should be logic low in the Sleep Mode.
See pin 18. See pin 18.
75 k MUTE 25 k
24
RSSI
A DC voltage proportional to the received signal strength is output from this pin. The output voltage range is 0.5V to 2.5V, into 51k load, and increases with increasing signal strength.
VCC
RSSI
25
FM OUT
Linear output from the FM demodulator. This pin is used in analog applications when signal fidelity is important. This output is inverted for low side injection of the LO and normal for high side injection.
FM OUT
26
DATA OUT
Demodulated data output from the demodulator. Output levels on this are TTL/CMOS compatible. The magnitude of the load impedance is intended to be 1M or greater. When using a RF2905 transmitter and receiver back to back a data inversion will occur, when the LO is low side injected. A high side injection will add an inversion of the Rx data.
DATA OUT
11-58
Rev B11 010516
RF2905
Pin 27 Function DEMOD IN Description
This pin is the input to the FM demodulator. This pin is NOT AC coupled. Therefore, a DC blocking capacitor is required on this pin to avoid shorting the demodulator input with the LC tank. A ceramic discriminator or DC blocked LC tank resonant at the IF should be connected to this pin.
Interface Schematic
VCC
10 k DEMOD IN
28
IF2 OUT
Balanced IF output from the 60dB limiting amplifier strip. This pin is intended to be connected to pin 27 through a 4pF (suggested) capacitor and an FM discriminator circuit.
IF2 OUT
29
VCC6
30
RESNTR+
This pin is used is supply DC bias to the second IF amplifier, Demodulator and Data Slicer. An IF bypass capacitor should be connected directly to this pin and returned to ground. A 10nF capacitor is recommended for 10.7MHz IF applications. This port is used to supply DC voltage to the VCO as well as to tune the center frequency of the VCO. Equal value inductors should be connected to this pin and pin 31 although a small imbalance can be used to tune in the proper frequency range.
ESNTR+
RESNTR-
4 k MOD IN
31 32
RESNTRVCC2
See RESNTR+ description.
See pin 30.
33 34
GND4 MOD IN
35
DIV CTRL
36
MOD CTRL
37
OSC SEL
38
OSC B2
This pin is used to select the prescaler modulus. A logic high (MOD CTRL>2.0V) selects 64 or 128 for the prescaler divisor. A logic low (MOD CTRL<1.0V) selects 65 or 129 for the prescaler divisor. Due to design timing constraints, the prescaler in the divide by 65 or 129 modes has a limited frequency range for accurate operation. These two modes are not recommended for use from 400MHz to 460MHz. A logic high (OSC SEL>2.0V) applied to this pin powers on reference oscillator 2 and powers down reference oscillator 1. A logic low (OSC SEL<1.0V) applied to this pin powers on reference oscillator 1 and powers down reference oscillator 2. This pin is connected directly to the reference oscillator 2 transistor base. The intended reference oscillator configuration is a modified Colpitts.
MOD CTL
OSC B1 OSC E
OSC B2
Rev B11 010516
11-59
TRANSCEIVERS
This pin is used is supply DC bias to the VCO, prescaler, and PLL. An RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications. GND4 is the ground shared on chip by the VCO, prescaler, and PLL electronics. FM analog or digital modulation can be imparted to the VCO through See pin 30. this pin. The VCO varies in accordance to the voltage level presented to this pin. To set the deviation to a desired level, a voltage divider referenced to Vcc is the recommended. This deviation is also dependent upon the overall capacitance of the external resonant circuit. This pin is used to select the desired prescaler divisor. A logic high (DIVCTRL>2.0V) selects the 64/65 divisor. A logic low DIV CTL (DIVCTRL<1.0V) selects the 128/129 divisor.
11
RF2905
Pin 39 40 41 Function OSC E OSC B1 LOOP FLT Description Interface Schematic
This pin is connected directly to the emitter of the reference oscillator See pin 38. transistors. This pin is connected directly to the reference oscillator 1 transistor See pin 38. base. The intended reference oscillator configuration is a modified Colpitts. Output of the charge pump, and input to the VCO control. An RC netVCC work from this pin to ground is used to establish the PLL bandwidth.
LOOP FLT
42 43
VREF P LOCK DET
Bypass pin for the prescaler reference voltage. A 33nF capacitor to ground is needed to suppress reference spurs in the device. This value may be different for different PCB arrangements. This pin provides an analog output indicating the lock status of the PLL. The amplitude of this signal is typically 200mVPP around a DC level of VCC-0.1V.
VCC 20 k LOCK DET
44
VCC1
45
PRESCL OUT
This pin is used to supply DC bias to the LNA, Mixer, first IF Amp, and Bandgap reference. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications. Dual-modulus/Dual-divide prescaler output. The output can be interfaced to an external PLL IC for additional flexibility in frequency programming.
PRESCL OUT
46
VCC3
11
TRANSCEIVERS
47
LVL ADJ
This pin is used to supply DC bias and collector current to the transmitter PA. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications. This pin is used to vary the transmitter output power. An output level adjustment range greater than 12dB is provided through analog voltage control of this pin. DC current of the transmitter power amp ia also reduced with output power. This pin MUST be low when the transmitter is disabled.
400
40 k LVL ADJ
4 k
48
PLL ENABL
This pin is used to power up or down the VCO and PLL. A logic high (PLLENABL>2.0V) powers up the VCO and PLL electronics. A logic low (PLLENABL<1.0V) powers down the PLL and VCO.
50 k PLL ENABL
11-60
Rev B11 010516
RF2905
RF2905 Theory of Operation and Application Information
The RF2905 is a part of a family of low-power RF transceiver IC's that was developed for wireless data communication devices operating in the European 433/ 868MHz ISM bands or 915MHz US ISM band.This IC has been implemented in a 15GHz silicon bipolar process technology that allows low-power transceiver operation in a variety of commercial wireless products. In its basic form, the RF2905 can implement a two-way half duplex FSK transceiver with the addition of some crystals, filters, and passive components. There are two reference crystals that allow for the transmit carrier and the receiver LO to be independently generated with a common PLL and VCO. The receiver IF section is optimized to interface with low cost 10.7MHz ceramic filters but has a -3 dB bandwidth of 25MHz and can still be used (with lower gain) at higher frequency with the other type of filters. The PA output and LNA input are available on separate pins and are designed to be connected together through a DC blocking capacitor. In the Transmit mode, the PA will have a 50 impedance and the LNA will be a high impedance. In Receive mode, the LNA will have a 50 interface and the PA will have a high impedance. This eliminates the need for a TX/RX switch and allows a single RF filter to be used in transmit and receive modes. Separate access to the PA and LNA allow the RF2905 to interface with external components such as higher power PA's, lower NF LNA's, upconverters, and downconverters for a variety of implementations. FM/FSK SYSTEMS The MOD IN pin drives an internal varactor for modulating the VCO. This pin can be driven with a voltage level needed to generate the desired deviation. This voltage can be carried on a DC bias to select the desired slope (deviation/volt) for FM systems. Or, a resistor divider network referenced to Vcc or ground can divide down logic level signals to the appropriate level for a desired deviation in FSK systems. On the receiver demod, two outputs are available, an analog FM output and a digital FSK output. The FM output is a buffered signal coming off of the quadrature demodulator. The digital output is generated by a data slicer that is DC coupled differentially to the demodulator. An on-chip 1.6MHz RC filter is provided at the demodulator output to filter the undesired 2xIF product. This balanced data slicer has a speed advantage over a conventional adaptive data slicer where a large capacitor is used to provide DC reference for bit decision. Since the balanced data slicer does not have to Rev B11 010516 charge a large capacitor, the RF2905 exhibits a very fast response time. For best operation of the on-chip data slicer, FM deviation needs to exceed the carrier frequency error anticipated between the receiver and transmitter with margin. The data slicer itself is a transconductance amp and the DATA OUT pin is capable of driving rail to rail output only into a very high impedance and small capacitance. The amount of capacitance will determine the bandwidth of the DATA OUT. At a 3pF load, the bandwidth is in excess of 500kHz. The rail to rail output of the data slicer is also limited by the frequency deviation and bandwidth of the IF filters. With the 180kHz bandwidth filters on the eval boards, the rail to rail output is limited to less than 140kHz. Choosing the right IF bandwidth and deviation vs. data rate (mod index) is important in evaluating the applicability of the RF2905 for a given data rate. While this type of data slicer is best for wideband deviation, it can also work for narrowband if care is taken to minimize frequency differences. By loading down the DATA OUT pin, the output will be limited to a small data signal on a DC carrier. With this signal, an external data slicer can be used to achieve higher data rates or improve performance in narrow deviations. Alternatively, an AFC loop can be added to correct for frequency errors with a few external components. For FM or FSK modulation, an internal varactor is used to directly modulate the VCO with the baseband data. The primary consideration when directly modulating the VCO is the data rate verses PLL loop bandwidth. The PLL will track out the modulation to the extent of its loop bandwidth which distorts the modulating data. Therefore, the lower frequency components of the modulating data should be 5 to 10 times the loop bandwidth to minimize the distortion. The lower frequency components are generated by long strings of 1's or 0's in the data stream. By limiting the number of consecutive, same bits, the lower frequency component can be set. In addition, the data stream should be balanced to minimize distortion. Using a coding pattern such as Manchester is highly recommended to optimize system performance. The PLL loop bandwidth is important in several other system parameters. For example, switching from transmit to receive requires the VCO to retune to another frequency. The switching speed is proportional to the loop bandwidth, the higher the loop bandwidth, the 11-61
11
TRANSCEIVERS
RF2905
faster the switching times. Phase noise of the VCO is another factor. Phase noise outside of the loop bandwidth is due to the noise of the VCO itself rather than the crystal reference. A design trade-off must be made here in selecting a PLL loop bandwidth with acceptable phase noise and switching characteristics and minimal distortion of the modulation data. AM/ASK SYSTEMS The transmitter of the RF2905 has an output power level adjustment (LVL ADJ) that can be used to provide approximately 18dB of power control for amplitude modulation. The RSSI output of the receiver section can be used to recover the modulation. The RSSI output is from a current source and needs to have a resistor to convert to a voltage. A 51k resistive load will produce an RSSI voltage of 0.7V to 2.5V, typically. A parallel capacitor is suggested to limit the bandwidth and filter noise. For ASK applications, the 18dB range of the LVL ADJ does not produce enough voltage swing in the RSSI for reliable communication. The OnOff keying (OOK) is suggested to provide reliable communications. To achieve this, both the LVL ADJ and TX ENABL need to be controlled together (please note that LVL ADJ cannot be left high when TX ENABL is low). This will provide a on/off ratio of >50dB. One unfortunate consequence of modulating this way is VCO pulling by the power amp. This results in a spurious output outside the desired transmit band as the PLL momentarily loses lock and reacquires. This can be avoided by pulse shaping the TX data to slow the change in the VCO load to a pace that the PLL can track with its given loop bandwidth. The loop bandwidth can also be increased to allow it to track faster changes due to load pulling. For the ASK/OOK receiver demodulator, an external data slicer is required. The RSSI output is used to provide both the filtered data and a very low pass filtered (relative to the data rate) DC reference to a data slicer. Because the very low pass filter has a slow time constant, a longer preamble may be required to allow for the DC reference to get to a stable state. Here, as in the case of the FSK transmitter, the data pattern also affects the DC reference and the reliability of the received data. Again, a coding scheme such as Manchester such should be used to improve data integrity. APPLICATION AND LAYOUT CONSIDERATIONS Both the RX IN and TX OUT have a DC bias on them. Therefore, DC blocking caps are required. If the RF filter has DC blocking characteristics like a ceramic dielectric filter, then only 1 DC blocking capacitor would 11-62 be needed to separate the DC of RX IN and TX OUT. These are RF signals and care should be taken to route these signals keeping them physically short. Because of the 50/high impedance nature of these two signals, they may be connected together into a signal 50 device such as a filter. An external LNA or PA can be used, if desired, but an external RX/TX switch may be required. The VCO is a very sensitive block in this system. RF signals feeding back into the VCO either radiated or coupled by traces may cause the PLL to become unlocked. The trace(s) for the anode of the tuning varactor should also be kept short. The layout of the resonators and varactor are very important. The capacitor and varactor should be closest to the RF2905 pins and the trace length should be as short as possible. The inductors can be placed further away and any trace inductance can be compensated by reducing the value of the inductors. Printed inductors may also be used with careful design. For best results, the physical layout should be as symmetrical as possible. Figure 1 is a recommended layout pattern for the VCO components. When using loop bandwidths lower than the 5kHz shown on the eval board, better filtering of the Vcc at the resonators (and lower Vcc noise as well) will help reduce phase noise of the VCO. A series resistor of 100 to 200 and a 1F or larger capacitor can be used.
Loop Voltage GND
11
TRANSCEIVERS
33 32 31 30 29 28
Not to Scale Representative of Size
GND
Vcc
Figure 1. Recommended VCO Layout For the interface between the LNA/mixer, the coupling capacitor should be as close to the RF2905 pins as possible with the bias inductor being further away. Once again, the value of the inductor can be changed to compensate to trace inductance. The output impedance of the LNA is in the order of several k which makes matching to 50 very hard. If image filtering is desired, a high impedance filter is recommended.
Rev B11 010516
RF2905
The quad tank of the discriminator can be implemented with ceramic discriminators available from a couple of sources. This design works well for wideband applications and where the temperature range is limited. The temperature coefficient of a ceramic discriminator can be in the order of +/- 50ppm per degree C. An automatic frequency control loop can be implemented using the DC level of the FM OUT for feedback to an external varactor on the reference crystal. An alternative to the ceramic discriminator is a LC tank. Figure 2 shows a schematic implementation of a LC tank. To lock faster, we need to minimize C. 1. To this end, use the divide by 128 rather than the 64, and a correspondingly lower frequency reference crystal to achieve the desired output frequency. 2. Design the loop filter for the minimum phase margin possible without causing loop instability problems; this allows C to be kept at a minimum. 3. Design the loop filter for the highest loop cut frequency possible without distorting low frequency modulation components; this also allows C to be kept at a minimum. CRYSTAL SELECTION Several issues arise in the selection of the crystals. Timing specifications such as start-up and switching are related to the crystal specifications, as well as external circuitry. The tolerance of the crystals are also an issue in optimum radio performance. In general, tighter tolerance crystals lead to better performance and are more critical to higher data rates. Frequency offsets between the TX crystal, RX crystal and discriminator generate duty cycle variations in the receive demodulator. The crystals used on the RF2905 evaluation boards are specified as a parallel resonant, 30pF crystal with a maximum ESR of 80. The initial tolerance is +20ppm and temperature stability is +30ppm for -10C to 70C. The transistor oscillator will work with a variety of different crystals and the final crystal specifications should be evaluated for each application. Faster start-up or switching times are achievable by specifying crystals with low motion inductance and low motional resistance. Additionally, the feedback caps of the oscillator can be changed to increase the voltage on the crystal. Generally, crystals in the leaded HC-49U packages will provide better start-up times than the smaller surface-mount types used on the evaluation board.
28 C17 7 pF 27 C16 10 nF 39 pF 3.3 H 4-22 pF R opt.
Figure 2. LC Type Discriminator Circuit
The DEMOD IN pin has a DC bias on it and must be DC blocked. This can be done either at the pin or at the ground side of the LC tank (this must also be done if a parallel resistor is used with a ceramic discriminator). The decision whether to used a LC or a ceramic discriminator should be based upon the frequency deviation in the system, discriminator Q needed, and frequency and temperature tolerances. Tuning of the LC tank is required to overcome the component tolerances in the tank. PREDICTING AND MINIMIZING PLL LOCK TIME The RF2905 implements a conventional PLL on chip, with a VCO followed by a prescaler dividing the output frequency down to be compared with a signal from the reference oscillator. The output of the phase discriminator is a sequence of pulse width modulated current pulses in the required direction to steer the VCO's control voltage to maintain phase lock, with a loop filter integrating the current pulses. The lock time of this PLL is a combination of the loop transient response time and the slew rate set by the phase discriminator output current combined with the magnitude of the loop filter capacitance. A good approximation for total lock time of the RF29.5 is: Lock time=D/fc+35000*C*dV Where D is a factor to account for the loop damping. For loops with low phase margin (30 to 40), use D=2 whereas for loops with better phase margin (50 to 60), use D=1. fc is the loop cut frequency. C is the sum of all shunt capacitors in the loop filter. dV is the required step voltage change to produce the desired frequency change during the transient. Rev B11 010516
11
TRANSCEIVERS
11-63
RF2905
Pin Out
PRESCL OUT PLL ENABL LOCK DET LOOP FLT OSC SEL 37 36 MOD CTRL 35 DIV CTRL 34 MOD IN 33 GND4 32 VCC2 31 RESNTR30 RESNTR+ 29 VCC6 28 IF2 OUT 27 DEMOD IN 26 DATA OUT 25 FM OUT 13 IF1 IN+ 14 IF1 IN15 IF1 BP+ 16 IF1 BP17 IF1 OUT 18 IF2 IN 19 GND6 20 VREF IF 21 IF2 BP+ 22 IF2 BP23 MUTE 24 RSSI LVL ADJ
OSC B1
48 RX ENABL 1 TX ENABL 2 TX OUT 3 GND2 4 RX IN 5 GND1 6 LNA OUT 7 GND3 8 MIX IN 9 GND5 10 MIX OUT+ 11 MIX OUT- 12
47
46
45
44
43
42
41
40
39
38
11
TRANSCEIVERS
11-64
OSC B2
VREF P
OSC E
VCC3
VCC1
Rev B11 010516
RF2905
Application Schematic 915MHz
VCC 10 4.7 uF 10 nF 22 pF 10 nF 22 pF 4.7 nH 5 pF 48 RX ENABL TX ENABL Filter 100 pF 3 5 100 pF VCC 10 10 nF VCC 10 8.2 H 10 nF 22 pF 11 pF Filter 10 nF Filter 10 nF 10 nF 10 nF 10 nF 10 nF
FM Disc.
3.9 k 47 nF 4.7 nH 2.7 k 100 pF
LOCK DET+
D1
TX DATA LVL ADJ PLL ENABL 47 46 34 Gain Control 31 30 41
3.3 nF
10 0.1 uF 100 100 pF pF 22 pF 10 nF
VCC
43 Lock Detector
42
40
39
38
44 32 22 pF
1 2
10 10 nF
VCC
Phase Detector & Charge Pump
Ref Select
37 45
OSC SEL PRESCL OUT MOD CTRL DIV CTRL
10 nH 7 22 pF 10 pF 9 11 12
Prescaler 128/129 or 64/65
36 35 24 25
Linear RSSI
FM OUT
26 13 14 15 16 17 18 20 21 22 28 5 pF 27 29 23 51 k
DATA OUT RSSI 10 pF
MUTE VCC
11
TRANSCEIVERS
D1 : SMV1233-011
PLL LOOP BANDWIDTH ~5 kHz
22 pF
10 nF
10
Rev B11 010516
11-65
RF2905
Application Schematic 868MHz
VCC 10 4.7 uF 10 nF 22 pF 10 nF 22 pF 6.8 nH 3 pF 48 RX ENABL TX ENABL Filter 100 pF 3 5 100 pF VCC 10 10 nF VCC 10 11 8.2 uH 12 10 nF 22 pF 11 pF Filter 10 nF Filter 10 nF 10 nF 10 nF
FM Disc.
3.9 k 47 nF 6.8 nH 2.7 k 100 pF
LOCK DET+
D1
TX DATA LVL ADJ PLL ENABL 47 46 34 Gain Control
3.3 nF
10 0.1 uF 100 100 pF pF 22 pF 10 nF
VCC
31
30
41
43 Lock Detector
42
40
39
38
44 32 22 pF
1 2
10 10 nF
VCC
Phase Detector & Charge Pump
Ref Select
37 45
OSC SEL PRESCL OUT MOD CTRL DIV CTRL
10 nH 7 22 pF 10 pF 9
Prescaler 128/129 or 64/65
36 35 24 25
Linear RSSI
FM OUT
26 13 14 15 16 17 18 20 21 22 28 5 pF 27 29 23 51 k
DATA OUT RSSI 10 pF
11
TRANSCEIVERS
D1 : SMV1233-011
10 nF
10 nF
MUTE VCC
PLL LOOP BANDWIDTH ~5 kHz
22 pF
10 nF
10
11-66
Rev B11 010516
RF2905
Application Schematic 433MHz
VCC 10 4.7 uF 10 nF 22 pF 10 nF 22 pF 27 nH 3 pF 48 RX ENABL TX ENABL Filter 100 pF 3 5 100 pF VCC 10 10 nF VCC 10 11 8.2 uH 12 10 nF 22 pF 11 pF Filter 10 nF Filter 10 nF 10 nF 10 nF 10 nF 10 nF
FM Disc.
3.9 k 47 nF 27 nH 2.7 k 100 pF
LOCK DET+
D1
TX DATA LVL ADJ PLL ENABL 47 46 34 Gain Control
3.3 nF
10 0.1 uF 100 100 pF pF 22 pF 10 nF
VCC
31
30
41
43 Lock Detector
42
40
39
38
44 32 22 pF
1 2
10 10 nF
VCC
Phase Detector & Charge Pump
Ref Select
37 45
OSC SEL PRESCL OUT MOD CTRL DIV CTRL
47 nH 7 22 pF 33 pF 9
Prescaler 128/129 or 64/65
36 35 24 25
Linear RSSI
FM OUT
26 13 14 15 16 17 18 20 21 22 28 5 pF 27 29 23 51 k
DATA OUT RSSI 10 pF
MUTE VCC
11
TRANSCEIVERS
D1 : SMV1233-011
PLL LOOP BANDWIDTH ~5 kHz
22 pF
10 nF
10
Rev B11 010516
11-67
RF2905
Evaluation Board Schematic
(Download Bill of Materials from www.rfmd.com.)
P1 P 1-1 1 2 P 1-3 3 T X E N A B L P 2-1 GND P LL E N A B L P 2-3 P2 1 2 3 LV L A D J GND N /C P 3-3 P 3-1 P3 1 2 3 M O D CTRL GND VCC S LIC E R IN R 10 50 k R 21 50 k C 28 10 nF C 40 33 nF LO C K D E T GND C 38 0.1 F R 16 TBD C 29 1nF R 11 1M
3 4 2
1
P4 1 P 4-2 P 4-3 P 4-4 P 4-5 2 3 4 5
GND RX ENABL O SC SEL D IV C T R L M U TE P 5-1
P5 1 2
U3 LM C 7211 R 18 TB D
5
LO C K D E T
Q1 2N 3904 C ircuit not populated. O ptional Lock D etector or O O K D ata S licer
R 12 10 VCC C 34 4.7 F C 32 10 nF C 33 22 pF
C 30 10 nF
C 31 22 pF R 23 0
C 41 3-10 pF X 2*
C 24 100pF
C 42 3-10 pF X 1*
C 26 3.3 nF R 9*
C 27 47nF
LV L A D J P LL E N A B L 48 RX ENABL TX ENABL C 1 100 pF 3 J1 RF L6* C 35* L7* C 36* C 39* C2 100 pF 4 5 6 L1* 7 C4 22 pF C 5* 9 10 11 L2 8.2 uH C6 10 nF C7 22 pF R4 8.2 k 12 C8 10 pF 13 R 15 0 C9 C 10 C 11 10 nF 10 nF 10 nF F1 S FE C V 10.7 M S 3S -A -T C B W =180kH z F2 S FE C V 10.7 M S 3S -A -T C B W =180kH z J2 M IX O U T 14 15 16 17 18 19 20 8 Linear RSSI P rescaler 128/129 or 64/65 1 2 G ain C ontrol 47 46 45 44 43 Lock D etector 42 41
C 25 C 23 100 pF100 pF 40 39 38 37 36 35 34 P hase D etector & C harge P um p 33 32 31 30 29 28 C 17 4 pF D IS C 27 C 16 10 nF 26 25 21 22 23 24 R5 51 k M UTE C 15 1 nF J3 R 22 N /C J4 FM O U T R8 0 C 18* D1 L5* L4* C 21 22 pF C 19 22 pF R 17 3.9 k
O SC SEL
M OD CTRL D IV C TR L J6 M O D IN VCC R7 10 C 22 10 nF C 20 10 nF R 6 10
R ef S elect
R1 10 VCC C3 10 nF
S M V 1233-011 R 13 1.5 k
R3 10
C D F107B -A 0.001 J5 D A TA O U T
11
TRANSCEIVERS
VCC
C 12 C 13 C 14 10 nF 10 nF 10 nF
S LIC E R IN
R 14 C 37 0 120 pF L3 2.2 H
Te st O n ly N ot P o p ula te d
2905400-, 401-, 402-
B oard L (433M H z) M (868M H z) H (915M H z)
C 35 (pF) 8 4 4
L6 (nH ) 22 8.2 8.2
L7 (nH ) 22 Jum per Jum per
C 39 (pF ) 8 N /C N /C
L1 (nH ) 47 10 10
C 5 (pF) 35 10 10
C 18 (pF) 3 5 5
L4,L5(nH ) 27 4.7 4.7
R 9 (k) 2.4 2.7 2.7
X 1 (M H z) 6.78 13.577344 7.15909
X 2 (M H z) 6.612 13.410156 7.07549
11-68
Rev B11 010516
RF2905
Evaluation Board Layout Board Size 3.05" x 3.05"
Board Thickness 0.031", Board Material FR-4, Multi-Layer (Same board layout is used for the -L, -M, and -H versions.)
11
TRANSCEIVERS
Rev B11 010516
11-69
RF2905
11
TRANSCEIVERS
11-70
Rev B11 010516
RF2905
11
TRANSCEIVERS
Rev B11 010516
11-71
RF2905
LNA S11
1.0
0.6
RXonTXoff
0.8
RXoffTXoff
Swp Max 1.2GHz
2.0
0.3GHz
-0.2
0.3GHz
-10.0
-0. 6
-0.8
.0 -2
1.0
TXonRXoff
RF OUT S22
0.6
-1.0
0.8
2.0
0 3.
TRANSCEIVERS
10.0 Swp Min 0.3GHz
-10.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
-0. 6
-0.8
11-72
-1.0
.0 -2
-3
.4 -0
-4. 0 -5.0
-0.2
4.0 5.0
0
.0
0.2
11
0.3GHz
-3
.4 -0
Swp Min 0.3GHz
Swp Max 1.2GHz
-4. 0 -5.0
10.0
.0
0.2
0.4
0.6
0.8
1.0
2.0
3.0
4.0 5.0
0
0. 4 0. 4
0 3.
4.0 5.0
0.2
10.0
4.0 5.0
10.0
Rev B11 010516
RF2905
2.5
RSSI Freq. = 915 MHz, VCC = 3.6V, RLoad = 51 k
Modulation Deviation Freq. = 915 MHz, VCC = 2.7 V, LVL ADJ = 2.7 V
600.0
500.0 2.0
Deviation From Carrier (kHz)
-100.0 -80.0 -60.0 -40.0
RSSI Output (Volts)
400.0
1.5
300.0
1.0
200.0
0.5 100.0
0.0 -120.0
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0
Received Power (dBm)
MOD IN (Volts)
Modulation Deviation Freq. = 915 MHz, VCC = 3.3 V, LVL ADJ = 3.3 V
600.0 1200.0
Modulation Deviation Freq. = 915 MHz, VCC = 5.0 V, LVL ADJ = 5.0 V
500.0
1000.0
Deviation From Carrier (kHz)
400.0
Deviation From Carrier (kHz)
800.0
300.0
600.0
200.0
400.0
100.0
200.0
11
0.0 1.0 2.0 3.0 4.0 5.0 6.0
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
0.0
MOD IN (Volts)
MOD IN (Volts)
Rev B11 010516
11-73
TRANSCEIVERS
RF2905
RX Mode Current versus VCC Freq = 905 MHz
12.00 10.00 9.00 Icc(mA) 8.00 7.00 10.00 30.00 35.00
TX Power Output and ICC versus VCC at 905 MHz, LVL ADJ = VCC
Power(dBm)
40.00
Icc (mA) 11.00
RF PO (dBm)
6.00 5.00 4.00 20.00 3.00 2.00 25.00
ICC (mA)
9.00
8.00
7.00 1.00 6.00 2.50 0.00 2.50
15.00
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
5.00
2.75
3.00
3.25
3.50
3.75
4.00
4.25
4.50
4.75
10.00 5.00
VCC (V)
VCC, LVL ADJ (V)
10.0
TX Power Output and ICC versus Level Adjust at 433 MHz, 3.6 V VCC
P out (dB) Icc (mA)
30.0
10.0
TX Power Output and ICC versus Level Adjust at 868 MHz, 3.6 V VCC
P out (dB) Icc (mA)
30.0
5.0
25.0
5.0
25.0
RF PO (dBm)
0.0
20.0
RF PO (dBm)
0.0
20.0
ICC (mA)
-5.0
15.0
-5.0
15.0
11
TRANSCEIVERS
-10.0
10.0
-10.0
10.0
-15.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
5.0
-15.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
5.0
LVL ADJ (V)
LVL ADJ (V)
10.0
TX Power Output and ICC versus Level Adjust at 905 MHz, 3.6 V VCC
P out (dB) Icc (mA)
30.0
5.0
25.0
RF PO (dBM)
0.0
20.0
-5.0
15.0
-10.0
10.0
-15.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
5.0
LVL ADJ (V)
11-74
ICC (mA)
Rev B11 010516
ICC (mA)
ICC (mA)

▲Up To Search▲

Price & Availability of RF2905

	To Download RF2905 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .